CYCLONE MAX
Figure 4-7: Qorivva Settings
4.1.2
4.1.3
26
BDM Shift Clock Delay Constant
The BDM Shift Clock Delay Constant allows the user to set the BDM shift
clock speed of the Cyclone MAX. The equation for determining the shifting
frequency is: 50000000 / (5 + 2*n). This clock cannot generally exceed a div 6
of the processor bus frequency.
Specify Programming Algorithm and S-Record
To specify the programming algorithm for the target, the user may simply
Cyclone MAX User Manual
相关PDF资料
D-1723-WH DRAWER SLIDING 16.56X6.31X19.18"
D072-0103 DEV KIT 7 NIMBLE SBC/FUSION7/BB
D10B2 SURGE SUPPR NETWORK BNC
D1U-12-CONC 12V D1U OUTPUT CONNECTOR CARD
D1U-48-CONC 48V D1U OUTPUT CONNECTOR CARD
D1U-52-CONC 52V D1U OUTPUT CONNECTOR CARD
D1U3CS-D-850-12-HC4C DC/DC FRNT END 850W 12V 3.3V AUX
D1U4CS-12-CONC CONNECTOR CARD D1U4CS OUTPUT
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